1. Technical Field
The present invention relates to data processing systems, and in particular to a method and system for improved synchronization of a data processing system""s components. Still more particularly, the present invention relates to a method and system for dynamic self-synchronization of data processing system components.
2. Description of the Prior Art
Synchronization among chip components of a data processing system is an important aspect of system performance. When chips are synchronized, they are able to execute similarly. However, if chips are not synchronized, then the same instruction takes place on different chips at different times. In present day data processing, it is desired to have systems which are deterministic, particularly for utilization with logical functions and flow which require orderly flow. Presently, most synchronization is handled via phase locked loop circuitry.
Phase-locked loop (xe2x80x9cPLLxe2x80x9d) circuits are electronic circuits utilized for locking an output signal in phase and frequency with a reference signal. In recent years, PLL circuits have often been employed in data processing systems and microprocessors for the purpose of generating a local clock signal that is phase-aligned with a reference clock signal generated by a crystal or another PLL circuit.
Typically, both the low-pass filter and the voltage control oscillator (VCO) of a PLL circuit employ analog components, and because of these analog components, PLL circuits are notoriously sensitive to environmental influences. In addition, there are also other sources that affect the performance of a PLL circuit, for example, a noisy or missing input reference signal, a noisy or missing output signal, a noisy or insufficient power supply to the PLL circuits, or extraneous noise picked up by the PLL circuit. Quite often, any one or more of the above factors may lead the PLL circuit output signal to lose lock with the input reference signal.
Another method of synchronizing clocks is by utilizing high speed clocks to synchronize the low speed clocks of the chips. With high speed clocks distributed to multiple chips within a system it is difficult to guarantee synchronization. Chips processes may become chaotic. Chips are to be run as fast as possible while keeping the clock frequencies high (within the chips). When data is transferred, a divided down clock is utilized between the chips. Traditionally, a divide-by-N circuit is utilized for the purpose of chip-to-chip communication. N represents an integer selected by the system developer. Divide-by-N circuits may yield one of N states. For example, a divide-by-four yields four different possibilities/states. Each state can be arbitrary and is affected by the way the individual chip is initialized and started. When chips are interconnected, one chip is unaware what the other chips are doing, resulting in potentially different states running simultaneously.
Data transmission systems or data processing systems generally demand a very high level of determinism. Due to the speed of the systems, a dynamic synchronization method is required to ensure this determinism is achieved. Presently, it is difficult to provide a method or system which provides this level of synchronization without a PLL.
It is therefore desirable to have a method and system for providing system synchronization. It is further desirable to have such a system and method wherein a system is synchronized dynamically by utilizing its internal components and clock circuitry to synchronize one chip with another.
In view of the foregoing, it is therefore one object of the present invention to provide an improved data processing system.
It is another object of the present invention to provide an improved method and system for improved synchronization of a data processing system""s components.
It is yet another object of the present invention to provide a method and system for dynamic self-synchronization of data processing system components.
The foregoing objects are achieved as is now described. A method and system for dynamic synchronization of a data processing system processor chips is disclosed. One of a plurality of chips is designated as a primary chip and all other chips as secondary chips. The clock phase of the chips are synchronized utilizing the primary chip""s clock phase as a reference clock phase for the secondary chips.
In one embodiment, a synchronization pattern is transmitted from the secondary chip to the primary chip. The pattern is received by the primary chip and retransmitted to the secondary chip. A state machine of the secondary chip logs the number of clock cycles required for the pattern to complete the round trip and compares the number of clock cycles to a predetermined value. The local clock of the secondary chip is adjusted based on the result of this comparison.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.